Patente US20060003525 - Circuit and method for a folded bit line memory cell with vertical ...

A memory cell for a memory array in a folded bit line configuration. The memory cell includes an access transistor formed in a pillar of single crystal semiconductor material. The access transistor has first and second source/drain regions and a body region that are vertically aligned. The access transistor...http://www.google.es/patents/US20060003525?utm_source=gb-gplus-sharePatente US20060003525 - Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor

Patentes

Circuit and method for a folded bit line memory cell with vertical ...