A method for manufacturing an integrated circuit on a semiconductor wafer is provided. The semiconductor wafer has complete die and partial die areas thereon. Functional circuit patterns are formed in a plurality of the complete die areas. The thermal absorption properties of the semiconductor wafer...http://www.google.es/patents/US6812550?utm_source=gb-gplus-sharePatente US6812550 - Wafer pattern variation of integrated circuit fabrication
Wafer pattern variation of integrated circuit fabrication
