A method for simulating a transistor circuit determines which nodes in the circuit change state in response to events, and then accurately computes the times at which those nodes change states. Using parasitic capacitance and transistor conductance values extracted from the circuit layout, this method...http://www.google.es/patents/US5305229?utm_source=gb-gplus-sharePatente US5305229 - Switch-level timing simulation based on two-connected components
Switch-level timing simulation based on two-connected components
