In an information processing system, a wait state signal is inserted into a RDY signal, according to which data are transmitted through memory and I/O buses. A CPU controls the number of the wait state signal to adjust the difference of the transfer speeds of the memory and I/O buses. An MCU (Memory...http://www.google.es/patents/US6065132?utm_source=gb-gplus-sharePatente US6065132 - Information processing system having a CPU for controlling access timings of separate memory and I/O buses
Information processing system having a CPU for controlling access timings of ...
