Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include p-channel non-volatile memory which has a first source/drain region and...http://www.google.es/patents/US20060234450?utm_source=gb-gplus-sharePatente US20060234450 - Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers
Programmable array logic or memory with p-channel devices and asymmetrical ...
