A multiple-gate memory cell comprises a semiconductor body and a plurality of gates arranged in series on the semiconductor body. A charge storage structure on the semiconductor body includes two charge trapping locations beneath each of all or some of the gates in the plurality of gates. Circuitry to...http://www.google.es/patents/US7106625?utm_source=gb-gplus-sharePatente US7106625 - Charge trapping non-volatile memory with two trapping locations per gate, and method for operating same
Charge trapping non-volatile memory with two trapping locations per gate ...
