A gated-delay locked loop that generates an output clock in phase with and having a frequency which is an integer multiple of the frequency of a reference clock. The gated delay-locked loop includes a voltage-controlled gated oscillator having first and second serially connected voltage-controlled delay...http://www.google.es/patents/US6208183?utm_source=gb-gplus-sharePatente US6208183 - Gated delay-locked loop for clock generation applications
Gated delay-locked loop for clock generation applications
