A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g....http://www.google.es/patents/US7564118?utm_source=gb-gplus-sharePatente US7564118 - Chip and wafer integration process using vertical connections
Chip and wafer integration process using vertical connections
