A device for dequantizing signals is provided in which two hardware operations are generated. The first hardware operation generates a signal representative of a binary function s(a,b) wherein the input signal b is shifted, incremented and decremented to provide signals 2b+1, 2b and 2b-1. A selector...http://www.google.es/patents/US5349545?utm_source=gb-gplus-sharePatente US5349545 - Arithmetic logic unit dequantization
