An FPGA architecture and method to reduce the size of the bitstream used in configuring or reconfiguring the FPGA. To facilitate features of the compression process, an FPGA is modified to implement an addressable data register in place of a conventional shift register. This allows data frames to be...http://www.google.es/patents/US6493862?utm_source=gb-gplus-sharePatente US6493862 - Method for compressing an FPGA bitsream
