A test system includes respective clock domain crossing circuits coupling memory device signals to a memory device being tested. The clock domain crossing circuit includes a ring buffer into which the respective memory device signal is latched responsive to a first clock signal. The particular buffer...http://www.google.es/patents/US7526704?utm_source=gb-gplus-sharePatente US7526704 - Testing system and method allowing adjustment of signal transmit timing
Testing system and method allowing adjustment of signal transmit timing
