A semiconductor integrated circuit device uses two keeper cells per configuration and/or enable bit as dual redundant storage with error detection thereof. One of the two keeper cells stores a logic level and the other keeper cell stores the inverse of that logic level before the integrated circuit device...http://www.google.es/patents/US20080238472?utm_source=gb-gplus-sharePatente US20080238472 - Low Power Mode Fault Recovery Method, System and Apparatus
Low Power Mode Fault Recovery Method, System and Apparatus
Número de solicitud: 12/017,521 Número de publicación: US 2008/0238472 A1 Fecha de presentación: 22 Ene 2008 Patente emitida: US7908516 ( Fecha de emisión 15 Mar 2011)
