A method used in fabrication of a recessed access device transistor gate has increased tolerance for mask misalignment. One embodiment of the invention comprises forming a vertical spacing layer over a semiconductor wafer, then etching the vertical spacing layer and the semiconductor wafer to form a...http://www.google.es/patents/US20070010058?utm_source=gb-gplus-sharePatente US20070010058 - Method and apparatus for a self-aligned recessed access device (RAD) transistor gate
Method and apparatus for a self-aligned recessed access device (RAD ...
Número de solicitud: 11/177,850 Número de publicación: US 2007/0010058 A1 Fecha de presentación: 8 Jul 2005 Patente emitida: US7282401 ( Fecha de emisión 16 Oct 2007)
