A memory controller couples 32-bit data words to and from a DRAM. The DRAM generates error checking and correcting syndromes to check and correct read data. The DRAM generates the syndromes from respective 128-bit data words each formed by 4 32-bit data words written to the DRAM, and thereby achieves...http://www.google.es/patents/US7526713?utm_source=gb-gplus-sharePatente US7526713 - Low power cost-effective ECC memory system and method
Low power cost-effective ECC memory system and method
