Processes are disclosed which facilitate improved high density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. In accordance with aspects of the invention, considerably greater numbers of die sites per wafer are achieved for 6 inch, 8 inch and 12 inch wafers for 4 M,...http://www.google.es/patents/US6288421?utm_source=gb-gplus-sharePatente US6288421 - Semiconductor memory circuitry including die sites for 16M to 17M memory cells in an 8" wafer
Semiconductor memory circuitry including die sites for 16M to 17M memory ...
