A simulation/debugging method for SOC designs that utilizes initial memory values loaded into a simulation model. A test program is then executed, and incremetal transaction records are generated for each incremental memory access (e.g., data write operations). Each transaction record includes a timestamp,...http://www.google.es/patents/US7437692?utm_source=gb-gplus-sharePatente US7437692 - Memory debugger for system-on-a-chip designs
