A method for substantially reducing conductive line cracking on an integrated circuit, comprising the steps of: obtaining a semiconductor structure with a first surface and with an insulating region adjacent to and rising above the first surface; and forming a layer of a first conductive material above...http://www.google.es/patents/US6093650?utm_source=gb-gplus-sharePatente US6093650 - Method for fully planarized conductive line for a stack gate
Method for fully planarized conductive line for a stack gate
