The present invention provides the method includes forming source/drain regions 170 in a semiconductor wafer substrate 110 adjacent a gate structure 130 located on a front side of the semiconductor wafer substrate 110. The source/drain regions 170 have a channel region 175 located between them. A first...http://www.google.es/patents/US7402535?utm_source=gb-gplus-sharePatente US7402535 - Method of incorporating stress into a transistor channel by use of a backside layer
Method of incorporating stress into a transistor channel by use of a ...
