An integrated circuit memory device is designed to perform high speed burst access read and write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new ...http://www.google.es/patents/US5729503?utm_source=gb-gplus-sharePatente US5729503 - Address transition detection on a synchronous design
Address transition detection on a synchronous design
