A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value...http://www.google.es/patents/US8089824?utm_source=gb-gplus-sharePatente US8089824 - Memory controller with staggered request signal output
Memory controller with staggered request signal output
