Techniques are provided for reducing power supply voltage drop introduced by routing conductive traces on an integrated circuit. Techniques for reducing variations in the power supply voltages received in different regions of an integrated circuit are also provided. Power supply voltages are routed within...http://www.google.es/patents/US6998719?utm_source=gb-gplus-sharePatente US6998719 - Power grid layout techniques on integrated circuits
Power grid layout techniques on integrated circuits
