Access to a buffer memory is provided by a controller architecture and method employing an arbiter state machine for control of data transfer between multiple external peripheral devices and the dynamic random access memory buffer. Data transfer channels for each peripheral device include a first-in,...http://www.google.es/patents/US5072420?utm_source=gb-gplus-sharePatente US5072420 - FIFO control architecture and method for buffer memory access arbitration
FIFO control architecture and method for buffer memory access arbitration
