A clock divider circuit and a system using the same. The clock divider circuit has a clock input coupled to receive an input clock signal having an input clock frequency. Clock division logic generates an output clock signal having a fifty percent duty cycle and an output clock frequency which is an...http://www.google.es/patents/US5914996?utm_source=gb-gplus-sharePatente US5914996 - Multiple clock frequency divider with fifty percent duty cycle output
Multiple clock frequency divider with fifty percent duty cycle output
