An integrated circuit wafer element and an improved method for bonding the same to produce a stacked integrated circuit. Plugs that extend from one surface of the wafer into the wafer are used to provide vertical connections and to bond the wafers together. A stacked integrated circuit is constructed...http://www.google.es/patents/US20040048459?utm_source=gb-gplus-sharePatente US20040048459 - Interlocking conductor method for bonding wafers to produce stacked integrated circuits
Interlocking conductor method for bonding wafers to produce stacked ...
Número de solicitud: 10/658,132 Número de publicación: US 2004/0048459 A1 Fecha de presentación: 8 Sep 2003 Patente emitida: US6838774 ( Fecha de emisión 4 Ene 2005)
