A semiconductor random access memory device is subjected to a parallel testing operation to see whether or not a defective memory cell is incorporated in the semiconductor random access memory device; in the parallel testing operation, a test bit of logic "1" level is sequentially written into a first...http://www.google.es/patents/US5436910?utm_source=gb-gplus-sharePatente US5436910 - Dynamic random access memory device having a parallel testing mode for producing arbitrary test pattern
Dynamic random access memory device having a parallel testing mode for ...
