When a test instruction signal is outputted from a command decoder, a test mode decoder receives the test instruction signal and outputs a test signal. When a DQM switch circuit receives the test signal, the DQM switch circuit outputs a mask/disable signal (MASK0 or MASK1) inputted to any one of two...http://www.google.es/patents/US6438667?utm_source=gb-gplus-sharePatente US6438667 - Semiconductor memory and memory system
