An arrangement in which resistors are interposed on a bus line to attenuate reflected spurious pulses. The resistors are positioned on the bus so as not to be between a processor and its cache memory, but so as to be between the combination of the processor and cache memory and components ...http://www.google.es/patents/US5805030?utm_source=gb-gplus-sharePatente US5805030 - Enhanced signal integrity bus having transmission line segments connected by resistive elements
Enhanced signal integrity bus having transmission line segments connected by ...
