A memory controller includes a check/correct circuit and a data remap circuit. The check/correct circuit is coupled to receive an encoded data block from a memory comprising a plurality of memory devices. The encoded data block includes a plurality of check bits, and the check/correct circuit is configured...http://www.google.es/patents/US6996766?utm_source=gb-gplus-sharePatente US6996766 - Error detection/correction code which detects and corrects a first failing component and optionally a second failing component
Error detection/correction code which detects and corrects a first failing ...
