Methods and devices to reduce processor-to-system memory access latency through the use of a memory buffer for the storage of cache lines flushed (cast out) from conventional level-1 (L1) and/or level-2 (L2) processor caches are described. The memory buffer, referred to as a cast-out cache, may be incorporated...http://www.google.es/patents/US20020042863?utm_source=gb-gplus-sharePatente US20020042863 - STORING A FLUSHED CACHE LINE IN A MEMORY BUFFER OF A CONTROLLER
STORING A FLUSHED CACHE LINE IN A MEMORY BUFFER OF A CONTROLLER
Número de solicitud: 09/363,789 Número de publicación: US 2002/0042863 A1 Fecha de presentación: 29 Jul 1999 Patente emitida: US6460114 ( Fecha de emisión 1 Oct 2002)
