A non-volatile memory system including an array of cells, each having an access transistor and a capacitor sharing a floating gate. The access transistors in each row are fabricated in separate well regions, which are independently biased. Within each row, the source of each access transistor is coupled...http://www.google.es/patents/US7522456?utm_source=gb-gplus-sharePatente US7522456 - Non-volatile memory embedded in a conventional logic process and methods for operating same
Non-volatile memory embedded in a conventional logic process and methods for ...
