A memory system having a plurality of DRAMs which are selectively provided non-inverted or inverted signals. The DRAMs have the ability to accept non-inverted or inverted address/command signals from a register that drives a plurality of signals simultaneously. The system includes DRAM receivers with...http://www.google.es/patents/US20050108468?utm_source=gb-gplus-sharePatente US20050108468 - MEMORY DEVICE WITH PROGRAMMABLE RECEIVERS TO IMPROVE PERFORMANCE
MEMORY DEVICE WITH PROGRAMMABLE RECEIVERS TO IMPROVE PERFORMANCE
Número de solicitud: 10/707,053 Número de publicación: US 2005/0108468 A1 Fecha de presentación: 18 Nov 2003 Patente emitida: US7646649 ( Fecha de emisión 12 Ene 2010)
