One aspect disclosed herein relates to a method for forming a programmable logic array. Various embodiments of the method include forming a first logic plane and a second logic plane, each including a plurality of logic cells interconnected to implement a logical function. Forming the logic cells includes...http://www.google.es/patents/US6794246?utm_source=gb-gplus-sharePatente US6794246 - Method for forming programmable logic arrays using vertical gate transistors
Method for forming programmable logic arrays using vertical gate transistors
