An electrically conductive layer or layer sequence preferably includes a metal-containing layer applied to a metal silicide or a polysilicon layer to reduce the resistance of buried bit lines. The layer or layer sequence has been patterned in strip form so as to correspond to the bit lines and is arranged...http://www.google.es/patents/US6794249?utm_source=gb-gplus-sharePatente US6794249 - Method for fabricating a memory cell
