A method of erasing a semiconductor nonvolatile memory (NVM) so as to compact the distribution of cell erased threshold voltages within a restricted range around a target erased threshold voltage. Erase pulses are applied to NVM cells until a determination is made by, for example, sensing total column...http://www.google.es/patents/US20040114437?utm_source=gb-gplus-sharePatente US20040114437 - Compaction scheme in NVM
Número de solicitud: 10/319,664 Número de publicación: US 2004/0114437 A1 Fecha de presentación: 13 Dic 2002 Patente emitida: US6836435 ( Fecha de emisión 28 Dic 2004)
