A programmable logic device architecture having a matrix of smaller functional units, each of which being a programmable logic array, and a set of fixed conductive lines connected to the functional unit inputs and outputs, the conductive lines forming programmable interconnection matrices. The input...http://www.google.es/patents/US5023606?utm_source=gb-gplus-sharePatente US5023606 - Programmable logic device with ganged output pins
