An SRAM cell consisting of a cross coupled transistors, a pair of transfer gate transistors and, a pair of load resistors, loading the cross-coupled transistors. Where soft error immunity is desired, the SRAM cell has a buried oxide layer isolating the devices from the silicon substrate. The load resistor...http://www.google.es/patents/US5578854?utm_source=gb-gplus-sharePatente US5578854 - Vertical load resistor SRAM cell
