There is provided an improved method for eliminating hot-carrier disturb during a read operation in a NAND memory architecture in which a floating gate device is used as a select gate. A first positive pulse voltage having a ramp-rate characteristic on its leading edge is applied to the drain...http://www.google.es/patents/US5815438?utm_source=gb-gplus-sharePatente US5815438 - Optimized biasing scheme for NAND read and hot-carrier write operations
Optimized biasing scheme for NAND read and hot-carrier write operations
