An EEPROM system having an array of memory cells that individually include two floating gates, bit line source and drain diffusions extending along columns, steering gates also extending along columns and select gates forming word lines along rows of floating gates. The dual gate cell increases the density...http://www.google.es/patents/US6266278?utm_source=gb-gplus-sharePatente US6266278 - Dual floating gate EEPROM cell array with steering gates shared adjacent cells
