A method for reducing memory latency in a multi-node architecture. In one embodiment, a speculative read request is issued to a home node before results of a cache coherence protocol are determined. The home node initiates a read to memory to complete the speculative read request. Results of a cache...http://www.google.es/patents/US7234029?utm_source=gb-gplus-sharePatente US7234029 - Method and apparatus for reducing memory latency in a cache coherent multi-node architecture
Method and apparatus for reducing memory latency in a cache coherent multi ...
