A risk of data garbling due to cumulative impact of disturbances occurring in memory areas in which no rewrite occurs is to be prevented. A memory device has an erasable and writable nonvolatile memory and a control circuit, wherein the control circuit is enabled to perform processing at a prescribed...http://www.google.es/patents/US7451266?utm_source=gb-gplus-sharePatente US7451266 - Nonvolatile memory wear leveling by data replacement processing
Nonvolatile memory wear leveling by data replacement processing
