A method and system for predicting delay of a multi-million gate sub-micron ASIC design is disclosed. The method and system include automatically partitioning a netlist into at least two logic cones, and running respective instances of a delay prediction application on the logic cones on at least two...http://www.google.es/patents/US7006962?utm_source=gb-gplus-sharePatente US7006962 - Distributed delay prediction of multi-million gate deep sub-micron ASIC designs
Distributed delay prediction of multi-million gate deep sub-micron ASIC designs
