A dynamic test generation method and apparatus enabling verification of the parallel instruction execution capabilities of VLIW processor systems is described. The test generator includes a user preference queue, a rules table, plurality of resource-related data structures, an instruction packer, and...http://www.google.es/patents/US6871298?utm_source=gb-gplus-sharePatente US6871298 - Method and apparatus that simulates the execution of paralled instructions in processor functional verification testing
Method and apparatus that simulates the execution of paralled instructions ...
