In a memory cell comprising a data cell array and a parity cell array, an error checking.multidot.correcting circuit is connected to each of the arrays through a selector. The selector is constituted by transistors connected to each of the bit lines in the memory cell. The number of circuit elements...http://www.google.es/patents/US5012472?utm_source=gb-gplus-sharePatente US5012472 - Dynamic type semiconductor memory device having an error checking and correcting circuit
Dynamic type semiconductor memory device having an error checking and ...
