Non-volatile semiconductor core memory performance is enhanced by reduced stress on core memory cells. Stress is reduced by selectable application of bias voltages to the sense line under control of the word line. The word line is connected to an inverting device in turn connected to a transistor effective...http://www.google.es/patents/US5434815?utm_source=gb-gplus-sharePatente US5434815 - Stress reduction for non-volatile memory cell
