A system and method for testing the placement of logic circuits on a regularly repeated array of integrated devices includes a base array memory, a basis memory, a floor plan memory, an array class memory, a logic cell index memory, a legal location index map memory, a legal location...http://www.google.es/patents/US5818726?utm_source=gb-gplus-sharePatente US5818726 - System and method for determining acceptable logic cell locations and generating a legal location structure
System and method for determining acceptable logic cell locations and ...
