A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) of an integrated circuit are provided. A first strain is applied to the channel region of the PFET but not the NFET via a lattice-mismatched semiconductor layer such as silicon germanium disposed in source and drain...http://www.google.es/patents/US20050029601?utm_source=gb-gplus-sharePatente US20050029601 - STRUCTURE AND METHOD OF MAKING STRAINED SEMICONDUCTOR CMOS TRANSISTORS HAVING LATTICE-MISMATCHED SOURCE AND DRAIN REGIONS
STRUCTURE AND METHOD OF MAKING STRAINED SEMICONDUCTOR CMOS TRANSISTORS ...
Número de solicitud: 10/604,607 Número de publicación: US 2005/0029601 A1 Fecha de presentación: 4 Ago 2003 Patente emitida: US6891192 ( Fecha de emisión 10 May 2005)
