The present invention is a memory circuit having a plurality of word lines, a plurality of bit line pairs, and memory cells disposed at the cross-position thereof. The memory comprises: a sense amplifier which is shared by the first bit line pair and the second bit line pair disposed in the column direction...http://www.google.es/patents/US6301173?utm_source=gb-gplus-sharePatente US6301173 - Memory device with faster reset operation
