A multi-purpose interface between a host computer and an FPGA. This interface uses an IEEE 1284 compliant EPP mode connection. When the host computer is initialized, a reset of the FPGA is carried out to clear the configuration memory of the FPGA. The data lines of the interface are then used to communicate...http://www.google.es/patents/US7206733?utm_source=gb-gplus-sharePatente US7206733 - Host to FPGA interface in an in-circuit emulation system
Host to FPGA interface in an in-circuit emulation system
