A set of memory cells can be erased by individually erasing portions of the set in order to normalize the erase behavior of each memory cell and provide more consistent erase rates. An erase voltage pulse can be applied to the set of memory cells with a first group of cells biased for erase and a second...http://www.google.es/patents/US7768826?utm_source=gb-gplus-sharePatente US7768826 - Methods for partitioned erase and erase verification in non-volatile memory to compensate for capacitive coupling effects
Methods for partitioned erase and erase verification in non-volatile memory ...
