A nonvolatile memory architecture (10) contains a plurality of memory arrays (12) formed by a plurality of floating gate memory cells and supports a 1X and 2X architecture. The nonvolatile memory design contains high voltage row decoders (16), low voltage row decoders (18), data multiplexors (24) and...http://www.google.es/patents/US5901086?utm_source=gb-gplus-sharePatente US5901086 - Pipelined fast-access floating gate memory architecture and method of operation
Pipelined fast-access floating gate memory architecture and method of operation
